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- Path: nntp.teleport.com!sschaem
- From: sschaem@teleport.com (Stephan Schaem)
- Newsgroups: comp.sys.amiga.programmer
- Subject: Re: TMapping again!
- Date: 17 Jan 1996 04:53:57 GMT
- Organization: Teleport - Portland's Public Access (503) 220-1016
- Message-ID: <4dhvd5$5r2@maureen.teleport.com>
- References: <4d0ou6$835@astfgl.idb.hist.no> <Z31Wx*zA0@mkmk.in-chemnitz.de> <4d42di$9e9@maureen.teleport.com> <4d5lvi$emc@brachio.zrz.TU-Berlin.DE> <4d6v0t$3dt@maureen.teleport.com> <4dg4jk$km@news.cs.tu-berlin.de>
- NNTP-Posting-Host: linda.teleport.com
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-
- Philipp Boerker (rawneiha@w255zrz.zrz.TU-Berlin.DE) wrote:
- : sschaem@teleport.com (Stephan Schaem) writes:
-
- : >Philipp Boerker (rawneiha@w352zrz.zrz.TU-Berlin.DE) wrote:
- : >: sschaem@teleport.com (Stephan Schaem) writes:
-
- : >: >Andre Weissflog (floh@mkmk.in-chemnitz.de) wrote:
- : >: >: In article <4d0ou6$835@astfgl.idb.hist.no>, Lasse Staff Jensen writes:
-
- : >: > I think he was mentiontioning this map code:
-
- : >: > REPEAT 32
- : >: >1) move.b (a0,d0.w),(a1)+
- : >: >2) addx.l d1,d0
- : >: > ENDR
-
- : >: The example above doesn't work anyway. You always need fraction
- : >: bits for both x- and y-adder.
-
- : > AAAAAA..........BBBBBCCCCCCDDDDD
-
- : > A = x fraction
- : > B = y integer
- : > C = y fraction
- : > D = x integer
- : > . = zero or more precision for x
-
- : > as you see the example above work...
-
- : Yes, I knew that one, but I never tried it because I doubt,
- : that it will have the accuracy needed. Or can you correct me?
-
- Acuracy of 6bit for Y. 1/64 is not that bad, it
- basicly mean you will repeat 1 pixel from the source upto 64time.
- 64x64 pixels are pretty huge, and for a 32x32 texture map 1/64
- should be enought for reduction.
-
- I never tryed myself,I use 256x256 tmap. and 16/16bit fixed point
-
- : >: Gee, how am I waiting for the 32 regs of the PPC... 8)
-
- : > Well, you are trading your nice addressing mode for this,
- : > no more (offset,base,offset*scale) ;) You will probably need
- : > an extra register and 3 instruction to emulate this on a ppc.
-
- : The PPC is fast enough to do some more ops between mem accesses
- : than 68k...
-
- Then you can do operation in betwen read if the dest register is not
- used by the folowing inst?
-
- : > dont know the PPC so I wont go into details :)
-
- : I do. The PPC isn't as RISC as most people fear. It's true
- : that there are only four address modes but they are as all
- : PPC instructions very powerful:
-
- : load/store register indirect
- : load/store register indirect with update
- : load/store register indirect indexed
- : load/store register indirect indexed with update
- : Are you missing something?
-
- scaling of the index for any work on array that are not bytes...
- For non time critical part I like/use all the 680x0 adr mode.
-
- pretty much what a 68000 is capable of, should be fun with a good
- macro assembler to work on that chip.
-
- Stephan
-
-